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update most target CPU features to llvm12 The tools/update_cpu_features script is coming along, and generates correct information for all these targets. The remaining targets are: * arm * aarch64 * amdgpu * riscv I will commit them once the issues with the updater tool are resolved.
2021-02-27 01:05:53 -07:00
//! This file is auto-generated by tools/update_cpu_features.zig.
const std = @import("../std.zig");
const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;
pub const Feature = enum {
vpu,
};
std.Target: Rename feature_set_fns to FeatureSetFns From https://ziglang.org/documentation/master/#Names: > If `x` is callable, and `x`'s return type is `type`, then `x` should > be `TitleCase`.
2024-08-11 12:58:47 +01:00
pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
update most target CPU features to llvm12 The tools/update_cpu_features script is coming along, and generates correct information for all these targets. The remaining targets are: * arm * aarch64 * amdgpu * riscv I will commit them once the issues with the updater tool are resolved.
2021-02-27 01:05:53 -07:00
pub const all_features = blk: {
std: update `std.builtin.Type` fields to follow naming conventions The compiler actually doesn't need any functional changes for this: Sema does reification based on the tag indices of `std.builtin.Type` already! So, no zig1.wasm update is necessary. This change is necessary to disallow name clashes between fields and decls on a type, which is a prerequisite of #9938.
2024-08-28 02:35:53 +01:00
const len = @typeInfo(Feature).@"enum".fields.len;
update most target CPU features to llvm12 The tools/update_cpu_features script is coming along, and generates correct information for all these targets. The remaining targets are: * arm * aarch64 * amdgpu * riscv I will commit them once the issues with the updater tool are resolved.
2021-02-27 01:05:53 -07:00
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
all: zig fmt and rename "@XToY" to "@YFromX" Signed-off-by: Eric Joldasov <bratishkaerik@getgoogleoff.me>
2023-06-15 13:14:16 +06:00
result[@intFromEnum(Feature.vpu)] = .{
update most target CPU features to llvm12 The tools/update_cpu_features script is coming along, and generates correct information for all these targets. The remaining targets are: * arm * aarch64 * amdgpu * riscv I will commit them once the issues with the updater tool are resolved.
2021-02-27 01:05:53 -07:00
.llvm_name = "vpu",
.description = "Enable the VPU",
.dependencies = featureSet(&[_]Feature{}),
};
const ti = @typeInfo(Feature);
update std lib and compiler sources to new for loop syntax
2023-02-18 09:02:57 -07:00
for (&result, 0..) |*elem, i| {
update most target CPU features to llvm12 The tools/update_cpu_features script is coming along, and generates correct information for all these targets. The remaining targets are: * arm * aarch64 * amdgpu * riscv I will commit them once the issues with the updater tool are resolved.
2021-02-27 01:05:53 -07:00
elem.index = i;
std: update `std.builtin.Type` fields to follow naming conventions The compiler actually doesn't need any functional changes for this: Sema does reification based on the tag indices of `std.builtin.Type` already! So, no zig1.wasm update is necessary. This change is necessary to disallow name clashes between fields and decls on a type, which is a prerequisite of #9938.
2024-08-28 02:35:53 +01:00
elem.name = ti.@"enum".fields[i].name;
update most target CPU features to llvm12 The tools/update_cpu_features script is coming along, and generates correct information for all these targets. The remaining targets are: * arm * aarch64 * amdgpu * riscv I will commit them once the issues with the updater tool are resolved.
2021-02-27 01:05:53 -07:00
}
break :blk result;
};
pub const cpu = struct {
refactor `update_cpu_features.zig` Most of this commit is whitespace changes, moving to use RLS for assigning the `CpuModel`
2024-11-25 00:06:14 -08:00
pub const generic: CpuModel = .{
update most target CPU features to llvm12 The tools/update_cpu_features script is coming along, and generates correct information for all these targets. The remaining targets are: * arm * aarch64 * amdgpu * riscv I will commit them once the issues with the updater tool are resolved.
2021-02-27 01:05:53 -07:00
.name = "generic",
.llvm_name = "generic",
update CPU features to LLVM 18 release/18.x branch, commit 78b99c73ee4b96fe9ce0e294d4632326afb2db42
2024-04-25 16:54:33 -07:00
.features = featureSet(&[_]Feature{
.vpu,
}),
update most target CPU features to llvm12 The tools/update_cpu_features script is coming along, and generates correct information for all these targets. The remaining targets are: * arm * aarch64 * amdgpu * riscv I will commit them once the issues with the updater tool are resolved.
2021-02-27 01:05:53 -07:00
};
};
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